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On-line error detection for tuning dynamic frequency scaling

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3 Author(s)
Neagu, M.-I. ; Tech. Univ. of Cluj-Napoca, Cluj Napoca, Romania ; Mois, G.D. ; Miclea, L.C.

The possibility of using residue codes for implementing a dynamic frequency scaling scheme (DFS) in Digital System Processing architectures with adders and or multipliers in the critical path is explored. Adders and multipliers provide the basic functionality of arithmetic operations in a wide variety of Digital Signal Processing algorithms.

Published in:

Automation Quality and Testing Robotics (AQTR), 2012 IEEE International Conference on

Date of Conference:

24-27 May 2012