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Block-based hardware scheduler design on Many-core architecture

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5 Author(s)
Lihan Ju ; Coll. of Comput. Sci., Zhejiang Univ., Hangzhou, China ; Ping Pan ; Baixing Quan ; Tianzhou Chen
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Because Moore's law is always still working and the requirement of energy-saving still exists, CPU architecture is becoming more and more complicated and developing to Many-core architecture. But many-core is incompatible with the current programming mode designed for single-core CPU. This paper proposed a Block level Hardware-based Scheduling on many-core architecture (BHS) by adding the program control information which combined with hard-ware design. With BHS, many-core can execute a variety of parallel styles for suiting parallel granularity. The two main features of BHS are: First, a block-based hardware scheduler was implemented to reduce the overhead of threads and get communication among cores faster; second, it is very applicable to small and scalable cores which were tightly coupled in the cores group, loosely coupled between groups in many-core architecture. And a variety of parallel techniques would be effectively exploited.

Published in:

Industrial Electronics (ISIE), 2012 IEEE International Symposium on

Date of Conference:

28-31 May 2012