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The recent popularity of three dimensional integrated circuits (3D ICs) technology stems from its higher integrated degree and enhanced performance. However, the design routability for 3D ICs becomes especially important. In this paper, we propose a novel estimation model and a congestion aware floorplan for 3D ICs. This model is based on probabilistic analysis considering through silicon vias (TSV) location and the congestion aware floorplan uses multiple criterions to judge a floorplan result. Experiments show the application of congestion aware floorplan can improve the routing congestion significantly with small increment of area and wirelength.