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Asynchronous Fine-Grain Power-Gated Logic

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2 Author(s)
Meng-Chou Chang ; Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan ; Wei-Hsiang Chang

This paper presents a novel low-power logic family, called asynchronous fine-grain power-gated logic (AFPL). Each pipeline stage in the AFPL circuit is comprised of efficient charge recovery logic (ECRL) gates, which implement the logic function of the stage, and a handshake controller, which handles handshaking with the neighboring stages and provides power to the ECRL gates. In the AFPL circuit, ECRL gates acquire power and become active only when performing useful computations, and idle ECRL gates are not powered and thus have negligible leakage power dissipation. The partial charge reuse (PCR) mechanism can be incorporated in the AFPL circuit. With the PCR mechanism, part of the charge on the output nodes of an ECRL gate entering the discharge phase can be reused to charge the output nodes of another ECRL gate about to evaluate, reducing the energy dissipation required to complete the evaluation of an ECRL gate. Moreover, AFPL-PCR adopts an enhanced C-element, called C*-element, in its handshake controllers such that an ECRL gate in AFPL-PCR can enter the sleep mode early once its output has been received by the downstream pipeline stage. To mitigate the hardware overhead of the AFPL circuit, two techniques of circuit simplification have been developed.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:21 ,  Issue: 6 )