Cart (Loading....) | Create Account
Close category search window
 

Asynchronous Fine-Grain Power-Gated Logic

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Meng-Chou Chang ; Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan ; Wei-Hsiang Chang

This paper presents a novel low-power logic family, called asynchronous fine-grain power-gated logic (AFPL). Each pipeline stage in the AFPL circuit is comprised of efficient charge recovery logic (ECRL) gates, which implement the logic function of the stage, and a handshake controller, which handles handshaking with the neighboring stages and provides power to the ECRL gates. In the AFPL circuit, ECRL gates acquire power and become active only when performing useful computations, and idle ECRL gates are not powered and thus have negligible leakage power dissipation. The partial charge reuse (PCR) mechanism can be incorporated in the AFPL circuit. With the PCR mechanism, part of the charge on the output nodes of an ECRL gate entering the discharge phase can be reused to charge the output nodes of another ECRL gate about to evaluate, reducing the energy dissipation required to complete the evaluation of an ECRL gate. Moreover, AFPL-PCR adopts an enhanced C-element, called C*-element, in its handshake controllers such that an ECRL gate in AFPL-PCR can enter the sleep mode early once its output has been received by the downstream pipeline stage. To mitigate the hardware overhead of the AFPL circuit, two techniques of circuit simplification have been developed.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 6 )

Date of Publication:

June 2013

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.