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Based on the stress extraction and measurement by the atomic-force-microscope-Raman technique with nanometer-level space resolution, the high compressive stress about 700 MPa on the Si critical dimension (CD) is observed in the current complementary metal-oxide-semiconductor (CMOS) transistor. The difference of thermal expansion between Si and Shallow trench isolation (STI) oxide during the total thermal budget for the standard CMOS transistor manufacture process results in this high compressive stress in Si CD and will further degrade the electron carrier mobility about 25% seriously. In order to relax this intrinsic-processed compressive stress in Si CD and recover this device performance loss, the novel process is proposed in this paper in addition to the usage of one-side pad-SiN layer demonstrated in our previous work. With this novel process of additional nitrogen-ion implantation (IMP) treatment in STI oxide, it can be found that the less compressive stress in the Si CD can be achieved by the smaller difference of thermal expansion coefficients between Si and highly n-doped SiO2 STI oxide. The formation of Si-N bonding in the STI-oxide region can be monitored by Fourier-transform infrared spectroscopy spectra, and the thermal expansion coefficients for Si, SiO2, and SiN are 2.6, 0.4, and 2.87 ppm/K, respectively. The relaxation of intrinsic-processed compressive stress in the Si CD of about 400 MPa by this proposed additional nitrogen IMP treatment contributes 14 % electron-carrier-mobility enhancement/recovery. The experimental electrical data agree well with the theoretical k.p calculation for the strained-Si theory.