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Synchronous digital systems have been presenting serious problems of implementation in DSM (deep sub-micron) VLSI technology, for which the asynchronous paradigm has become an interesting alternative. Unfortunately, the topic of synthesis of asynchronous digital systems has been ignored or presents only a few numbers of teaching classes in most courses in electrical engineering, due the difficulty of different styles of asynchronous design, what requires many hours of classroom teaching. In this paper we propose a methodology for synthesis of asynchronous systems that requires just few hours of classroom teaching, being interesting to be incorporated in the subject of logic design. Starting from the RTL (Register Transfer Level) description of synchronous systems, the proposed method synthesizes the asynchronous system in the “decomposition” style, which is defined by XBM_AFSM (extended burst-mode asynchronous finite state machine) + datapath synchronous. A simple procedure is used to convert the specification of SFSM to the XBM specification, which describes the XBM_AFSM. Through a case study, it is shown the simplicity of the methodology, resulting in high-performance circuits.