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Hybrid scheme for low-power set associative caches

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2 Author(s)
Calagos, M. ; Electr. Eng., Univ. of Texas Pan American, Edinburg, TX, USA ; Chu, Y.

Proposed is a dual-mode-access cache to reduce power consumption in set associative caches for embedded systems. The proposed scheme introduces a pre-cache buffer to determine how to access the cache. This is a buffered dual-mode cache scheme. The proposed cache shows better prediction rates and lower power consumption than conventional caches, such as the phased cache or the way-prediction cache. Cacti and Simplescalar simulators have been used for these simulations using SPEC2000 benchmark programs. Experimental results show that the proposed cache reduces power consumption by an average of 19.7% over conventional caches.

Published in:

Electronics Letters  (Volume:48 ,  Issue: 14 )