Cart (Loading....) | Create Account
Close category search window

ATM network interface architectures for low latency

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sundstrom, P. ; Dept. of Inf. Technol., Lund Univ., Sweden ; Andersson, P.

There are many important factors to consider when designing a network interface for an ATM network, and different applications have different demands. This paper addresses the problem of making an ATM interface with the focus on very low message latency, e.g., for shared memory multiprocessors on top of a network of workstations, and yet making it general enough to be a cost effective solution. Different approaches to the interface are evaluated and an architecture where critical functions are distributed and performed in dedicated hardware, integrated with, or very close to, the processors, are proposed

Published in:

Computer Communications and Networks, 1997. Proceedings., Sixth International Conference on

Date of Conference:

22-25 Sep 1997

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.