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Fast error detection through efficient use of hardwired resources in FPGAs

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2 Author(s)
Gabriel L. Nazar ; Instituto de Informática, Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, Brazil ; Luigi Carro

Providing high reliability for FPGAs is a demanding task, as such devices may be subject to faults in the configuration bitstream, altering the specified function. Traditional modular redundancy remains the most used technique, due to its high fault coverage and low performance overhead. When high availability and strict real-time deadlines must be considered, however, a short mean time to repair also becomes crucial. The use of fine-grained modules can accelerate error detection, fault diagnosis and bitstream correction, but with increased area costs. In this work, we propose the use of hardwired resources found in state-of-the-art FPGAs to provide fast and area efficient fine-grained error detection. Experimental results show an average speed up in error detection of 7.68 times with only 3.2% more area overhead, when compared to coarse-grained modular redundancy.

Published in:

2012 17th IEEE European Test Symposium (ETS)

Date of Conference:

28-31 May 2012