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Nanoscale VLSI design faces unprecedented reliability challenges in the presence of prevalent catastrophic defects, soft errors and parametric variations. We construct minimum logic networks of guaranteed single soft error resilience by combining error detection and clock gating, and leveraging an existing fault-secure logic design technique, which is to construct group-sliced logic networks with outputs in group distance-two code. We propose two construction methods for minimum group distance-two code and minimum logic networks with outputs in a group distance-two code, respectively. Our experimental results show that we achieve guaranteed single soft error resilient logic networks of an average of 1.63× area, 1.63× critical path delay, and 2.17× power consumption, while DMR achieves an average of 2.12× area, 1.26× critical path delay, and 2.79× power consumption compared with the minimum area design.