Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Clerc, S. ; STMicroelectron., Crolles, France ; Abouzeid, F. ; Gasiot, G. ; Gauthier, D.
more authors

A 32kb memory is presented with an Ultra Low Voltage optimized 10 transistors bitcell designed to withstand an extended voltage range from 1.2V down to 0.35V, achieving 1.77pJ low energy access. A validation circuit was fabricated in 65nm CMOS and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts show 0.32V minimum voltage at 490kHz and up to 17X energy gain per operation. The memory terrestrial radiation Soft Error Rate was characterized with no multibit errors reported, enabling future medical appplications radiation reliability through bit-interleaving combined with error correcting code.

Published in:

IC Design & Technology (ICICDT), 2012 IEEE International Conference on

Date of Conference:

May 30 2012-June 1 2012