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System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors

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2 Author(s)
Ahmet Ceyhan ; Electrical and Computer Engineering Department, Georgia Institute of Technology, Atlanta, USA ; Azad Naeemi

This paper presents the first system-level study on the impact of carbon nanotube field-effect transistors (CNFETs) on multilevel interconnect networks. In this paper, for the first time, the gains in speed and energy-delay product (EDP) offered by CNFETs over CMOS are presented as a function of interconnect length. It is demonstrated that the respective 4.3× and 8× improvements in intrinsic delay and EDP of CNFET inverters at 16nm technology node over Si-CMOS inverters are quickly overshadowed by the delay and EDP of interconnects. For repeater-inserted interconnects, the delay and EDP improvements of CNFETs saturate at 2.08× compared to CMOS. However, CNFETs offer a major advantage in terms of the required number of metal levels in a multilevel interconnect network because of the availability of a larger number of repeaters compared to Si-CMOS switches.

Published in:

2012 IEEE International Conference on IC Design & Technology

Date of Conference:

May 30 2012-June 1 2012