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A CMOS sub-harmonic frequency synthesizer suitable for V-band applications is presented in this letter. By employing distributed switches, the output swing of the voltage- controlled oscillator can be significantly enhanced while maintaining sufficient frequency tuning range for the second-harmonic extraction. With a direct injection-locked divide-by-two circuit and current-mode-logic dividers as the prescaler stage, a nested 2/3-cell-based retimed programmable counter is adopted for frequency synthesis. Based on the proposed architecture, a 30 GHz frequency synthesizer is implemented using a 0.18 μm standard CMOS process.
Date of Publication: Aug. 2012