By Topic

Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)

Planar fully-depleted SOI technology is becoming mainstream within STMicroelectronics, targeting modern mobile and consumer multimedia markets. This technology combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolutionary step from conventional planar bulk CMOS. At 28nm, we find that planar FD more than matches the peak performance of “G”-type bulk technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors. FD implementation of a representative design offers 1.6×-7× speedup compared to bulk across a range of supply voltages.

Published in:

Faible Tension Faible Consommation (FTFC), 2012 IEEE

Date of Conference:

6-8 June 2012