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In this paper we present a novel CMOS pass transistor logic style for ultra low-voltage and high speed digital applications. The circuits presented offer more than 90% delay reduction compared to conventional CMOS for supply voltages less than 400mV. Differential AND and NAND pass transistor gates presented and compared to complementary pass transistor logic CPL. Simulated data obtained by the H spice simulation and relevant for 90nm TSMC process are provided.
Faible Tension Faible Consommation (FTFC), 2012 IEEE
Date of Conference: 6-8 June 2012