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A Bayesian-based process parameter estimation using IDDQ current signature

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2 Author(s)
Shintani, M. ; Dept. of Commun. & Comput. Eng., Kyoto Univ., Kyoto, Japan ; Sato, T.

Post-fabrication performance compensation and adaptive delay testing are effective means to improve yield and reliability of LSIs. In these methods, process parameter estimation plays a key role. In this paper, we propose a novel technique for accurate on-chip process parameter estimation. The proposed technique is based on Bayes' theorem, in which on-chip parameters, such as threshold voltages, are estimated by current signatures obtained within a regular IDDQ testing. No additional circuit and additional measurements are required for the purpose of estimation. Numerical experiments demonstrate that the proposed technique can achieve less than 10 mV accuracy in estimating threshold voltages.

Published in:

VLSI Test Symposium (VTS), 2012 IEEE 30th

Date of Conference:

23-25 April 2012