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Design and evaluation of a high throughput robust router for network-on-chip

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3 Author(s)
Alhussien, A. ; Dept. of Electr. Eng. & Comput. Eng., Univ. of California-Irvine, Irvine, CA, USA ; Wang, C. ; Bagherzadeh, N.

Network-on-chip (NoC) systems have been proposed to achieve high-performance computing where multiple processors are integrated into one chip. As the number of cores increases and the chips are scaled in the deep submicron technology, the NoC systems become subject to physical manufacture defects and running-time vulnerability, which result in faults. The faults affect the performance and functionality of the NoC systems and result in communication malfunctions. In this study, a fault tolerant router design with an adaptive routing algorithm that tolerates faults in the network links and the router components is proposed. The approach does not require the use of virtual channels and assures deadlock freedom. Furthermore, the experimental results show that the proposed architecture can tolerate multiple failures and prove robustness and fault tolerance with negligible impact on the performance.

Published in:

Computers & Digital Techniques, IET  (Volume:6 ,  Issue: 3 )