By Topic

Hardware-Accelerated Simulation Environment for CT Sigma–Delta Modulators Using an FPGA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Bruckner, T. ; Institute of Microelectronics, University of Ulm, Ulm, Germany ; Lorenz, M. ; Zorn, C. ; Becker, J.
more authors

In this brief, a hardware-accelerated simulation environment for continuous-time (CT) \Sigma \Delta modulators is presented. Due to the presence of the nonlinear quantizer, simulating \Sigma \Delta modulators is a complicated task in general. The simulation of CT modulators is even more time consuming than that of their discrete-time counterparts, due to the analog loop filter. In particular, in an automated design environment, a large number of simulations have to be performed during the design process of  \Sigma \Delta modulators. In this brief, it is shown for the first time that the system-level emulation of CT \Sigma \Delta modulators on an field-programmable gate array results in a significant acceleration, reducing the simulation time by a factor of more than \hbox {10}^{5} compared to a commonly used Simulink simulation. This allows simulating 10 000 of modulators per second, enabling the use of heuristic search algorithms for real-time design for CT \Sigma \Delta modulators.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 8 )