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Redistribution of Electrical Interconnections for Three-Dimensional Wafer-Level Packaging With Silicon Bumps

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4 Author(s)
Guoqiang Wu ; State Key Lab. of Transducer Technol., Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, China ; Dehui Xu ; Bin Xiong ; Yuelin Wang

In this letter, an approach to the redistribution of electrical interconnections is investigated for potential application in 3-D wafer-level packaging. A cap wafer with silicon bumps and electrical feedthroughs is bonded together with a device wafer using wafer-level glass-frit bonding technology. During the bonding process, the mechanical bond is performed by glass-frit bonding to form hermetic packaging. Simultaneously, the silicon bumps provide close contact for the electrical feedthroughs on the cap wafer and the metal pads on the device wafer, on which a gold-aluminum eutectic is formed to achieve electrical interconnections between the cap wafer and the device wafer. Moreover, the silicon bumps provide a way to control well the height of the bonding materials. This process not only realizes a wafer-level hermetic sealing but also achieves the redistribution of electrical interconnections. Application of this approach for a high performance MEMS resonator is demonstrated, which illustrates the feasibility of this process.

Published in:

Electron Device Letters, IEEE  (Volume:33 ,  Issue: 8 )