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Enhancing Hysteresis in Graphene Devices Using Dielectric Screening

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3 Author(s)
Kevin Brenner ; Nanoelectronics Research Center, Georgia Institute of Technology, Atlanta, GA, USA ; T. J. Beck ; James D. Meindl

A method of increasing hysteresis in graphene devices with a dielectric coating is presented. By controlling the sweep direction of the gate bias, “high-conductance” and “low-conductance” states can be produced by transitioning the device between dielectric screened and unscreened states, which is a fundamentally new approach to producing hysteresis. Moderate carrier densities (4 × 1012 cm-2) result in field-driven injection of charge from the graphene channel into the underlying SiO2 substrate, modifying the scattering charged-impurity layout seen by the graphene, ultimately disrupting the steady-state screening process. A stable room-temperature conductance gap of nearly one order of magnitude is demonstrated.

Published in:

IEEE Electron Device Letters  (Volume:33 ,  Issue: 8 )