By Topic

Test data compression based on Variable Prefix Dual-Run-Length Code

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yang Yu ; Dept. of Autom. Test & Control, Harbin Inst. of Technol., Harbin, China ; Zhiming Yang ; Xiyuan Peng

Higher circuit densities in System-on-a-Chip (SoC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. In order to reduce the volume of SoC test data, an improved FDR code was proposed, called Variable Prefix Dual-Run-Length Code. This coding scheme has two steps: firstly, the don't care bits in the test data are filled with 0s or 1s using the Dynamic Programming Algorithm (DPA); then according to the novel partition way, the test data was divided as alternate runs of 0's and 1's, and the 0 runs and 1 runs was encoded. Due to its simple architecture, the decompression circuit for this proposed code needs only little additional hardware. Experimental results for the ISCAS'89 benchmark circuits show that the proposed code outperforms other similar codes in achieving higher compression ratio and requiring smaller area overhead for the on-chip decoder.

Published in:

Instrumentation and Measurement Technology Conference (I2MTC), 2012 IEEE International

Date of Conference:

13-16 May 2012