Does the low hole transport mass in <110> and <111> Si nanowires lead to mobility enhancements at high field and stress: A self-consistent tight-binding study

The hole surface roughness and phonon limited mobility in the silicon <100>, <110>, and <111> square nanowires under the technologically important conditions of applied gate bias and stress are studied with the self-consistent Poisson-sp3d5s*-SO tight-binding bandstructure method. Under an applied gate field, the hole carriers in a wire undergo a volume to surface inversion transition diminishing the positive effects of the high <110> and <111> valence band nonparabolicities, which are known to lead to the large gains of the phonon limited mobility at a zero field in narrow wires. Nonetheless, the hole mobility in the unstressed wires down to the 5 nm size remains competitive or shows an enhancement at high gate field over the large wire limit. Down to the studied 3 nm sizes, the hole mobility is degraded by strong surface roughness scattering in <100> and <110> wires. The <111> channels are shown to experience less surface scattering degradation. The physics of the surface roughness scattering dependence on wafer and channel orientations in a wire is discussed. The calculated uniaxial compressive channel stress gains of the hole mobility are found to reduce in the narrow wires and at the high field. This exacerbates the stressed mobility degradation with size. Nonetheless, stress gains of a factor of 2 are obtained for <110> wires down to 3 nm size at a 5×10¹² cm^–2 hole inversion density per gate area.