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In this paper we present the results of the implementation of a nanoscale double-gate (DG) MOSFET compact model, which includes hydrodynamic transport model, in Verilog-A in order to carry out circuit simulation. The model in Verilog-A is used with the SMASH circuit simulator for the analysis of the DC and transient behavior electrical CMOS circuits. A template device representative for a downscaled symmetric double-gate MOSFET was used to validate the model. A CMOS inverter has been analyzed. Comparison between the drift-diffusion (DD) and hydrodynamic transport model within the practical range of bias voltages has been highlighted.