A high speed A/D converter for using in low power CMOS image sensors

This paper presents a high speed, high resolution column-parallel ADC with global digital error correction. Proposed A/D converter is suitable for using in high-frame-rate CMOS image sensors. This new method has more valuable than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11-bit ADC is implemented in 0.25 μm CMOS technology. Moreover, an overall SNR of 63.8 dB can be achieved at 0.5 Msample/s. The power dissipation of all 320 column-parallel ADCs with the peripheral circuits consume 76 mW at 2.5V supplies.