By Topic

A high speed A/D converter for using in low power CMOS image sensors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Teymouri, M. ; Innovation Res. Center, Urmia Univ. of Technol., Urmia, Iran ; Alizadeh, B. ; Dadashi, A. ; Mahmoudi, A.

This paper presents a high speed, high resolution column-parallel ADC with global digital error correction. Proposed A/D converter is suitable for using in high-frame-rate CMOS image sensors. This new method has more valuable than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11-bit ADC is implemented in 0.25 μm CMOS technology. Moreover, an overall SNR of 63.8 dB can be achieved at 0.5 Msample/s. The power dissipation of all 320 column-parallel ADCs with the peripheral circuits consume 76 mW at 2.5V supplies.

Published in:

Mixed Design of Integrated Circuits and Systems (MIXDES), 2012 Proceedings of the 19th International Conference

Date of Conference:

24-26 May 2012