FPGA implementation of chaotic state sequence generator for secure communication

In this work, a hardware implementation of Chaotic State Sequence Generator for Secure Communication is proposed. The state of the chaotic generator is quantized by a threshold detector and fed to the 16-bit shift register which stores states at sixteen different time instants. The state selection corresponding to any one of the 16 time instant is performed by a multiplexer in pseudo-random manner using a Finite State Machine. The designs were coded in VHDL, implemented on a FPGA device and successfully tested for image encryption application.