By Topic

A high-throughput and size-efficient NoC buffer design method

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Wenbiao Zhou ; ASIP Inst., Beijing Inst. of Technol., Beijing, China ; Zhenyu Liu ; Yanjun Zhang ; Siye Wang
more authors

This paper presents a high-throughput and size efficient buffer design method for an application specific NoC. The method firstly configures on chip buffer according with the mapping position of IP and the routing path of communication pairs, then computes the minimum value of buffer's size under NoC performance guarantee. Under the same buffer size, the experiments show that the method results in the 40% improvement of the throughput when compared the common input buffer design method.

Published in:

Systems and Informatics (ICSAI), 2012 International Conference on

Date of Conference:

19-20 May 2012