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A low power low noise OTA with adjustable gain PID feedback network

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2 Author(s)
de Oliveira Dutra, O. ; UniFEI-Univ. Fed. de Itajuba, Itajuba, Brazil ; Pimenta, T.C.

This work describes a 0.5 μm CMOS implementation of a Folded Cascode OTA designed for minimum Input Referred Noise for non-implantable EEG SoC arrays. It is also described a small area PID feedback network using a high resistive pMOS pseudo-resistor and small integration capacitances for programmable gain control throughout parasitic insensitive nMOS switches. Simulation results show that it achieves about 2.2 μVrms of input referred noise for 6 μA of total current at ± 1.8 V supply voltage. The circuit provides a NEF of 4.55 within a 1.96 kHz bandwidth and midband gain of 40.22 dB.

Published in:

Microelectronics (MIEL), 2012 28th International Conference on

Date of Conference:

13-16 May 2012

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