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We propose and demonstrate a relaxed-SiGe/sSi enhancement-mode gate stack for quantum dots. The wafers are grown to our specification using CVD process by Lawrence SQI. The devices were fabricated within a 150 mm Si foundry setting that uses implanted ohmics and chemical-vapor-deposited dielectrics. Polysilicon depletion gates are used to form few electron dots in the sSi quantum well. High density plasma silicon dioxide was used as a secondary dielectric, followed by a tungsten/titanium nitride enhancement gate to draw electrons into the system. A modified implant, polycrystalline silicon formation and annealing conditions were utilized to minimize the thermal budget that potentially leads to Ge/Si interdiffusion.