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Integration of III-V on Si for High-Mobility CMOS

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14 Author(s)

In this paper we present results from an InGaAs/InP implant free quantum well device integrated fully in a Si CMOS processing line. The virtual InP substrates are generated using a Si template which is prepared by standard STI processing. The Si in the STI trenches is etched and a Ge seed layer grown.

Published in:

Silicon-Germanium Technology and Device Meeting (ISTDM), 2012 International

Date of Conference:

4-6 June 2012