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Sub-word handling in data-parallel mapping

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5 Author(s)
Psychou, G. ; Comp. Syst. Dept., RWTH Aachen Univ., Aachen, Germany ; Fasthuber, R. ; Catthoor, F. ; Hulzink, J.
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Data-parallel processing is a widely applicable technique, which can be implemented on different processor styles, with varying capabilities. Here we address single or multi-core data-parallel instruction-set processors. Often, handling and reorganisation of the parallel data may be needed because of diverse needs during the execution of the application code. Signal word-length considerations are crucial to incorporate because they influence the outcome very strongly. This paper focuses on the broader solution space of selecting sub-word lengths (at design time) including especially hybrids, so that mapping on these data parallel single/multi-core processors is more energy-efficient. Our goal is to introduce systematic exploration techniques so that part of the designers effort is removed. The methodology is evaluated on a representative application driver for a number of data-path variants and the most promising trade-off points are indicated. The range of throughput-energy ratios among the different mapping implementations is spanning a factor of 2.2.

Published in:

ARCS Workshops (ARCS), 2012

Date of Conference:

28-29 Feb. 2012