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A SPT Treatment to the Realization of the Sign-LMS Based Adaptive Filters

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4 Author(s)
Sunav Choudhary ; Department of Electrical Engg., University of Southern California, Los Angeles, USA ; Pritam Mukherjee ; Mrityunjoy Chakraborty ; Shakti Shankar Rath

The “sum of power of two (SPT)” is an effective format to represent filter coefficients in a digital filter which reduces the complexity of multiplications in the filtering process to just a few shift and add operations. The canonic SPT is a special sparse SPT representation that guarantees presence of at least one zero between every two non-zero SPT digits. In the case of adaptive filters, as the coefficients are updated with time continuously, conversion to such canonic SPT forms is, however, required at each time index, which is quite impractical and requires additional circuitry. Also, as the position of the non-zero SPT terms in each coefficient word changes with time, it is not possible to carry out multiplications involving the coefficients via a few fixed “shift and add” operations. This paper addresses these problems, in the context of a SPT based realization of adaptive filters belonging to the sign-LMS family. Firstly, it proposes a bit serial adder that takes as input two numbers in canonic SPT and produces an output also in canonic SPT, which is then extended to the case where one of the inputs is given in 2's complement form. This allows weight updating purely in the canonic SPT domain. It is also shown how the canonic SPT property of the input can be used to reduce the complexity of the proposed adder. For multiplication, the canonic SPT word for each coefficient is partitioned into non-overlapping digit pairs and the data word is multiplied by each pair separately. The fact that each pair can have at the most one non-zero digit is exploited further to reduce the complexity of the multiplication.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:59 ,  Issue: 9 )