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We present a novel structure for the back-side readout silicon photomultiplier (SiPM). Current SiPMs are front-illuminated structures with front-side readout, which have relatively small geometric fill factor leading to degradation in their photon detection efficiency (PDE). Back-side readout devices will provide an advantageous solution to achieve high PDE. We designed and investigated a novel structure that would allow back-side readout while creating a region of high electric field optimized for avalanche breakdown. In addition, this structure has relatively high fill factor and also allows the direct coupling of the individual microcell of the SiPM to application-specific integrated circuits. We will discuss the performance that can be attained with this structure through device simulation and the process flow that can be used to fabricate this structure through process simulation.