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Low power soft output Viterbi decoder scheme for turbo code decoding

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3 Author(s)
Lang Lin ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong ; Chi Ying Tsui ; Cheng, R.S.

Turbo codes, which are new forward error-correcting codes (FEC), represent a prospective coding scheme for future wireless communication. In this paper, we propose two schemes to reduce the power consumption of the register-exchange soft output Viterbi decoder (SOVD) for turbo code decoding. The first scheme employs the notion of the scarce state transition (SST) which changes the data representation during decoding. The second scheme simply changes the bit representation in the survivor memory unit (SMU) of the decoder. Simulation results show that up to 70% reduction in bit transitions in the SMU can be achieved by both schemes when decoding a 16-state turbo code

Published in:

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on  (Volume:2 )

Date of Conference:

9-12 Jun 1997