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Harvard architecture uses physically separate memories for their instructions and data. In the case of a flash memory with a buffer system, separate data and instruction buffers can lead to diversification of a flash architecture and achieve the high performance by overcoming effectively the limitations of a unified buffer. So, the proposed NAND flash system is composed of two separate buffers for exploiting the characteristics inherent in each module. Also, we propose a new operating mechanism for reducing overhead of flash memory, that is, erase and write operations. According to our simulation results, the write operations and the erase operations are about 60% and 68% less than other unified buffer systems with two times more space, respectively. And also, the average memory access tine is improved by about 70% compared with other unified buffer systems.