We present the development of a front end amplifier and discriminator circuit implemented in two successive nodes of commercial CMOS process, namely 90 nm and 130 nm. The aim of this work is two-fold, firstly to examine new technology features such as increased transconductance and transit frequency resulting in higher speed at lower power consumption, and secondly to prototype a novel front end architecture developed to maintain high dynamic range and open loop gain in the presence of the degradation of intrinsic transistor gain and low supply voltage accompanying the scaling of CMOS processes. The circuits are intended to work with silicon strip detectors of moderate length. Although both versions are optimized for 5 pF input capacitance, the input stage of 130 nm front end can be biased with a current allowing for readout of detectors with capacitances of the order of 10 pF. Special attention has been given to the comparison of noise performance and matching of the channel gain and discriminator offsets. Although both versions show good basic analog performance in terms of speed and gain, an appreciable difference in the channel-to-channel matching and the noise figures is measured. The ENC performance of 130 nm version of the amplifier follows theoretical predictions confirming no excess noise for the devices used, whilst the noise performance of the 90 nm version is noticeably worse. Looking at the difference in noise performance between the two designs, the 130 nm process is better understood and is thus a more appropriate choice for the current upgrade project. As a consequence, the presented 130 nm design will form the core of the ABC130 chip for the ATLAS SCT upgrade.