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Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT

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3 Author(s)
Mohanty, B.K. ; Dept. of Electron. & Commun. Eng., Jaypee Univ. of Eng. & Technol., Guna, India ; Mahajan, A. ; Meher, P.K.

We have suggested a new data-access scheme for the computation of lifting two-dimensional (2-D) discrete wavelet transform (DWT) without using data transposition. We have derived a linear systolic array directly from the dependence graph (DG) and a 2-D systolic array from a suitably segmented DG for parallel and pipeline implementation of 1-D DWT. These two systolic arrays are used as building blocks to derive the proposed transposition-free structure for lifting 2-D DWT. The proposed structure requires only a small on-chip memory of (4N + 8P) words and processes a block of P samples in every cycle, where N is the image width. Moreover, it has small output latency of nine cycles and does not require control signals which are commonly used in most of the existing DWT structures. Compared with the best of the existing high-throughput structures, the proposed structure requires the same arithmetic resources but involves 1.5N less on-chip memory and offers the same throughput rate. ASIC synthesis result shows that the proposed structure for block size 8 and image size 512 512 involves 28% less area, 35% less area-delay product, and 27% less energy per image than the best of the corresponding existing structures. Apart from that, the proposed structure is regular and modular; and it can be easily configured for different block sizes.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 7 )