By Topic

Simple noise model and low-noise data-output buffer for ultrahigh-speed memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wada, T. ; Mitsubishi Electr. Corp., Hyogo, Japan ; Eino, M. ; Anami, K.

An analytic noise (voltage bounce on chip-internal VCC/GND lines) model for data-output buffers is described. The model indicates that tr (switching time of output transistor) greater than L×G0 (product between the parasitic inductance on VCC/GND lines and the conductance of the output transistor) and small output voltage amplitude are required in order to reduce the noise voltage. The model give VLSI circuit designers a rough estimation of the VCC/CND line noise. A low-noise data-output buffer combined with a voltage down converter (VDC) is proposed. It decreases the peak noise voltage by one-half without degrading the access time

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 6 )