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A p-well GaAs MESFET technology for mixed-mode applications

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2 Author(s)
Canfield, P.C. ; Hewlett-Packard Co., Santa Rosa, CA, USA ; Allstot, D.J.

A device structure consisting of an ion-implanted n-channel buried between an implanted p- region at the surface and an implanted p-region under the channel is presented. The deep p-layer (p-well) is extended beyond the source region of the MESFET and independently contacted through an ohmic p+ diffusion. In normal operation, the source and p-well (backgate) terminals are electrically shorted together, as in silicon CMOS technology. By using junction isolation rather than conventional resistive isolation, the p-well n-channel MESFETs are free of trap-related parasitic effects including drain current transients with very long time constants, low-frequency frequency-dependent small-signal drain conductance, sidegating between neighboring devices, light sensitivity, etc. While eliminating these classical MESFET problems, the radiofrequency performance of the p-well GaAs MESFET remains comparable to the conventional n-channel device

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 6 )

Date of Publication:

Dec 1990

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