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Parallel prefix adders are used for efficient VLSI implementation of binary number additions. Ling architecture offers a faster carry computation stage compared to the conventional parallel prefix adders. Recently, Jackson and Talwar proposed a new method to factorize Ling adders, which helps to reduce the complexity as well as the delay of the adder further. This paper discusses the design and implementation details for such lower complexity, fast parallel prefix adders based on Ling theory of factorization. In particular, valency or radix, the number of inputs to a single node, is explored as a design parameter. Several low and high valency adders are implemented in 65 nm CMOS technology. Experimental results show that the high-valency Ling adders have superior area×delay characteristics over previously reported Ling-based or non-Ling adders for the same input size. Moreover, our 20-bit high valency adder has a better area×delay measurement than the previously-published 16-bit adders.
Date of Conference: 18-20 April 2012