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In this paper, we present a flow for integrating hardware descriptions into Simulink simulations. It enables the automatic generation of a Simulink component out of a hardware component model given as RT level VHDL. The approach is based on two steps. The first step transforms the VHDL model to SystemC. In contrast to existing VHDL-to-SystemC transformation tools, the readability and configurability of the input model is preserved. In addition, our approach yields a more exact model, as a custom designed VHDL-like data-type system is employed. The second step generates a specific wrapper to allow the use of the component in a Simulink simulation. This transformation strategy will be evaluated with two industrial automotive electronics hardware designs.
Date of Conference: 18-20 April 2012