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A fully asynchronous digital signal processor using self-timed circuits

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2 Author(s)
Jacobs, G.M. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Brodersen, R.W.

A complete, microprocessor-based, general-purpose digital signal processor (DSP) was designed and fabricated using self-timed circuits following a four-cycle handshake protocol to provide fully asynchronous operation without the need for any global clock. The methodology developed allows modular design, as has been traditionally performed in clocked systems. Versions of the DSP included an FIR (finite impulse response) filter, and IIR (infinite impulse response) filter, and a test program exercising all mathematical and control functionality. All operated correctly and showed cycle times comparable to clocked designs in the same technology. The DSP, designed in 2-μm n-well CMOS, has an active area of 6.6 mm×4.7 mm, and instruction times range from 73 to 337 ns at 5 V, depending on the hardware requirements of each operation

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 6 )