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Process variation compensation with effective gate-width tuning for low-voltage CMOS digital circuits

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4 Author(s)
Kishiwada, Y. ; Div. of Electr., Electron. & Inf. Eng., Osaka Univ., Suita, Japan ; Ueda, S. ; Miyawaki, Y. ; Matusoka, T.

Recently, as CMOS devices become smaller, process variation, especially threshold voltage variation, significantly influences circuit characteristics under lower supply voltage. This paper proposes a process variation compensation technique with effective gate-width tuning as well as body biasing.

Published in:

Future of Electron Devices, Kansai (IMFEDK), 2012 IEEE International Meeting for

Date of Conference:

9-11 May 2012