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Co-evaluation of power supply noise of CMOS microprocessor using on-board magnetic probing and on-chip waveform capturing techniques

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4 Author(s)
Sasaki, Y. ; Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan ; Yoshikawa, K. ; Nagata, M. ; Ichikawa, K.

On-chip and on-board power noise measurements were performed on a 32-bit microprocessor core in a 90-nm CMOS technology. The on-chip voltage noise and on-board near-field magnetic field measurements are related to each other with a unified power delivery network that is formed by on-chip and on-board parasitic components. The significant importance of LSI chip-package-board co-simulation is also discussed from the measurement results.

Published in:

Future of Electron Devices, Kansai (IMFEDK), 2012 IEEE International Meeting for

Date of Conference:

9-11 May 2012