By Topic

Test Metrics Model for Analog Test Development

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Stratigopoulos, H.G. ; TIMA Lab., Univ. Joseph Fourier, Grenoble, France

The trend nowadays is to integrate more and more functionalities into a single chip. This, however, has serious implications in the testing cost. Especially for the analog circuits, the testing cost tends to be very high, despite the fact they occupy a small fraction of the area of the chip. Therefore, to reduce this cost, there is a high interest to replace the most demanding tests by alternative measurements. However, such replacement may inadvertently result in accepting faulty chips or rejecting functional chips. In this paper, we present a method for estimating such test metrics in the general scenario where a single test is replaced by a single measurement. The method is based on the extreme value theory and the statistical blockade algorithm. It can be readily applied during the test development phase to obtain estimates of the test metrics and corresponding confidence intervals with parts-per-million precision. For this purpose, the method requires a small number of selective simulations that we can afford to run in practice.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:31 ,  Issue: 7 )