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A methodology for the design of multichannel, wideband, highly efficient hybrid Class-J power amplifiers for fourth-generation (4G) communication transmitters is proposed. The design procedure is based on the automatic generation and evaluation of a vast number of output matching networks of the same topology but different dimensions, with respect to efficiency, output power, and linearity. The approach can find application in the management of the efficiency/linearity/bandwidth tradeoff in amplifier design. In this paper, two matching network architectures have been considered. One multistubbed network and a stepped-impedance microstrip line network. The approach has been validated through the design, simulation, and measurement of two power amplifiers realized using the aforementioned procedure. The first amplifier covers 1.6-2.2 GHz (31.6% fractional bandwidth) with 55%-68% drain efficiency at the 2-dB compression point and worst case adjacent channel power ratio (ACRP) and error vector magnitude (EVM) of - 21.8 dBc and 8.35%, respectively, over the bandwidth. The second covers 0.5-1.8 GHz (113% fractional bandwidth) with 50%-69% drain efficiency at the 2-dB compression point and worst case ACRP of - 27.5 dBc and EVM of 4.22%. Both amplifiers are based on a commercial, packaged 10-W GaN HEMT transistor.