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A digital SQUID with the feedback loop closed on chip was simulated, designed, fabricated and tested. The basic architecture of a delta modulator A/D converter with coarse quantization was implemented using a latching comparator and a write gate which acts in conjunction with the pickup loop as an integrator. The digital data stream was amplified at 4.2 K using a current amplifier stage, a voltage driver gate and a GaAs FET impedance transformer. The analog input signal was reconstructed at room temperature by integrating the data stream using a 17 bit up/down counter at a clock frequency of about 10 MHz. Noise measurements of the D/A converted signal have been taken indicating that bit errors cause a 1/f/sup 2/ like excess noise. Numerical simulations have been performed in parallel to the design and experimental verification. Operation margins of all gates, except for the voltage driver have been estimated using a circuit-orientated simulator. Models to estimate noise and linearity of the feedback loop arrangement have been developed.