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A 10-b 50-MHz CMOS D/A converter with 75-Ω buffer

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1 Author(s)
Pelgrom, M.J.M. ; Philips Res. Lab., Eindhoven, Netherlands

A 10-b 50-MHz digital-to-analog (D/A) converter for video applications that is based on a dual-ladder resistor string is presented. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces the glitch energy, and signal-dependent switch signals reduce high-frequency distortion. The output buffer allows driving 1 Vpp to 75 Ω. The chip consumes 65 mW at maximum clock frequency and a full-swing output signal. The device is processed in a standard 1.6-μm CMOS process with a single 5-V supply voltage. The double-ladder architecture allows the requirements for small cell area and high linearity to be separated. Compensation techniques have been applied to reduce the second- and third-order distortion components; at 5-MHz signal frequency the total harmonic distortion is -53 dB

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 6 )

Date of Publication:

Dec 1990

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