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An optical data transfer system has been designed by analyzing an equivalent-circuit model for a silicon photonic chip to determine how to enhance the system gain and suppress intersymbol interference (ISI). This robust system uses three-valued logic (3VL), which is achieved by using a 1-bit delay in the Tx portion and a set-reset (SR) latch in the Rx portion. Use of the 3VL protocol results in less ISI than use of the conventional two-valued one at high bit rates. The system is also robust against internal ac coupling.