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Analysis of electronic carrier traps in Cr-SrTiO3-based charge trap flash memory devices

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4 Author(s)
Yujeong Seo ; School of Electronics Engineering, Korea University, Seoul 136-701, South Korea ; Yeong Song, Min ; Park, Soyun ; Geun Kim, Tae

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.4729127 

We investigated the deep-level traps formed in Cr-SrTiO3/Si3N4/SiO2 structures deposited on n-type Si by deep-level transient spectroscopy (DLTS). Three electron traps, with averaged activation energies of 0.24, 0.28, and 0.53 eV, were observed below the conduction band minimum of Si. Different behaviors in the dependence of DLTS on both filling bias and pulse confirm that the traps originate as the Si3N4 bulk trap, the Si3N4/SiO2 interfacial trap, and the Si/SiO2 interfacial trap. We also demonstrate that a specific point defect is the source of memory behavior in Cr-SrTiO3-based fusion-type charge trap flash (CTF) memory devices.

Published in:

Applied Physics Letters  (Volume:100 ,  Issue: 24 )

Date of Publication:

Jun 2012

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