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Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation

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3 Author(s)
Devlin, B. ; Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan ; Ikeda, M. ; Asada, K.

We present a low overhead technique that can be used to offset both large systematic and random process delay variation in the near-threshold voltage operation region. We present an analysis of this this technique applied to a 65nm CMOS self synchronous FPGA that is capable of operation from 2.0V to 0.37V. By using dual voltage supplies, we can offset gate-level pipeline stages that show large delay variation, to achieve energy savings per operation of up to 102x for a 200 stage pipeline.

Published in:

Cool Chips XV (COOL Chips), 2012 IEEE

Date of Conference:

18-20 April 2012

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